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91 relations: Advanced Vector Extensions, AES instruction set, AltiVec, Analog Devices, ARM architecture, Atmel, Atmel AVR instruction set, AVR32, Benchmark (computing), Bit, Bit Manipulation Instruction Sets, Blackfin, Branch (computer science), Byte, CDC Cyber, Cell (microprocessor), Central processing unit, Comparison of CPU microarchitectures, Complex instruction set computer, Computer architecture, DEC Alpha, DLX, Elbrus 2000, Endianness, ESi-RISC, Explicitly parallel instruction computing, F16C, FMA instruction set, IA-32, IBM, IBM System/360, IBM System/360 architecture, IBM System/370, Instruction set architecture, Intel 8080, Intel MCS-51, Itanium, Java virtual machine, Jazelle, Lattice Semiconductor, LatticeMico32, List of instruction sets, M32R, MDMX, Microprocessor, MIPS architecture, MIPS-3D, MMIX, MMX (instruction set), MOS Technology 6502, ..., Motorola 68000, Motorola 68000 series, Multimedia Acceleration eXtensions, NS320xx, OpenRISC, Operand, PA-RISC, PDP-11, Physical Address Extension, PowerPC, Processor design, Processor register, Reduced instruction set computer, Register file, Register window, RISC-V, RX microcontroller family, S+core, SPARC, SSE2, SSE3, SSE4, Stack machine, Streaming SIMD Extensions, SuperH, Synopsys, Transmeta Crusoe, Transputer, VAX, Visual Instruction Set, X86, X86-64, X87, XOP instruction set, Z/Architecture, Zilog Z80, 16-bit, 32-bit, 3DNow!, 64-bit computing, 8-bit. Expand index (41 more) »
Advanced Vector Extensions
Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011.
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AES instruction set
Advanced Encryption Standard instruction set (or the Intel Advanced Encryption Standard New Instructions; AES-NI) is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.
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AltiVec
AltiVec is a single-precision floating point and integer SIMD instruction set designed and owned by Apple, IBM, and Freescale Semiconductor (formerly Motorola's Semiconductor Products Sector) — the AIM alliance.
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Analog Devices
Analog Devices, Inc., also known as ADI or Analog, is an American multinational semiconductor company specializing in data conversion and signal processing technology, headquartered in Norwood, Massachusetts.
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ARM architecture
ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments.
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Atmel
Atmel Corporation is an American-based designer and manufacturer of semiconductors, founded in 1984.
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Atmel AVR instruction set
The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996.
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AVR32
The AVR32 is a 32-bit RISC microcontroller architecture produced by Atmel.
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Benchmark (computing)
In computing, a benchmark is the act of running a computer program, a set of programs, or other operations, in order to assess the relative performance of an object, normally by running a number of standard tests and trials against it.
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Bit
The bit (a portmanteau of binary digit) is a basic unit of information used in computing and digital communications.
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Bit Manipulation Instruction Sets
Bit Manipulation Instructions Sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD.
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Blackfin
The Blackfin is a family of 16- or 32-bit microprocessors developed, manufactured and marketed by Analog Devices.
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Branch (computer science)
A branch is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order.
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Byte
The byte is a unit of digital information that most commonly consists of eight bits, representing a binary number.
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CDC Cyber
The CDC Cyber range of mainframe-class supercomputers were the primary products of Control Data Corporation (CDC) during the 1970s and 1980s.
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Cell (microprocessor)
Cell is a multi-core microprocessor microarchitecture that combines a general-purpose Power Architecture core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.
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Central processing unit
A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.
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Comparison of CPU microarchitectures
The following is a comparison of CPU microarchitectures.
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Complex instruction set computer
A complex instruction set computer (CISC) is a computer in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single instructions.
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Computer architecture
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.
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DEC Alpha
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 32-bit VAX complex instruction set computer (CISC) ISA.
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DLX
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).
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Elbrus 2000
The Elbrus 2000, E2K (Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
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Endianness
Endianness refers to the sequential order in which bytes are arranged into larger numerical values when stored in memory or when transmitted over digital links.
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ESi-RISC
eSi-RISC is a configurable CPU architecture from Ensilica.
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Explicitly parallel instruction computing
Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the HP–Intel alliance to describe a computing paradigm that researchers had been investigating since the early 1980s.
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F16C
The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.
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FMA instruction set
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations.
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IA-32
IA-32 (short for "Intel Architecture, 32-bit", sometimes also called i386) is the 32-bit version of the x86 instruction set architecture, first implemented in the Intel 80386 microprocessors in 1985.
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IBM
The International Business Machines Corporation (IBM) is an American multinational technology company headquartered in Armonk, New York, United States, with operations in over 170 countries.
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IBM System/360
The IBM System/360 (S/360) is a family of mainframe computer systems that was announced by IBM on April 7, 1964, and delivered between 1965 and 1978.
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IBM System/360 architecture
The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture.
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IBM System/370
The IBM System/370 (S/370) was a model range of IBM mainframe computers announced on June 30, 1970 as the successors to the System/360 family.
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Instruction set architecture
An instruction set architecture (ISA) is an abstract model of a computer.
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Intel 8080
The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974.
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Intel MCS-51
The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computer (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems.
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Itanium
Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64).
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Java virtual machine
A Java virtual machine (JVM) is a virtual machine that enables a computer to run Java programs as well as programs written in other languages and compiled to Java bytecode.
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Jazelle
Jazelle DBX (Direct Bytecode eXecution) is an extension that allows some ARM processors to execute Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes.
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Lattice Semiconductor
Lattice Semiconductor Corporation is an American manufacturer of high-performance programmable logic devices (FPGAs, CPLDs, & SPLDs).
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LatticeMico32
LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs).
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List of instruction sets
A list of computer central processor instruction sets: (By alphabetical order by its manufacturer.).
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M32R
The M32R is a 32-bit RISC instruction set architecture (ISA) developed by Mitsubishi Electric for embedded microprocessors and microcontrollers.
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MDMX
The MDMX (MIPS Digital Media eXtension), also known as MaDMaX, is an extension to the MIPS architecture released in October 1996 at the Microprocessor Forum.
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Microprocessor
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits.
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MIPS architecture
MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA)Price, Charles (September 1995).
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MIPS-3D
MIPS-3D is an extension to the MIPS V instruction set architecture (ISA) that added 13 new instructions for improving the performance of 3D graphics applications.
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MMIX
MMIX (pronounced em-mix) is a 64-bit reduced instruction set computing (RISC) architecture designed by Donald Knuth, with significant contributions by John L. Hennessy (who contributed to the design of the MIPS architecture) and Richard L. Sites (who was an architect of the Alpha architecture).
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MMX (instruction set)
MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1997 with its P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology".
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MOS Technology 6502
The MOS Technology 6502 (typically "sixty-five-oh-two" or "six-five-oh-two") William Mensch and the moderator both pronounce the 6502 microprocessor as "sixty-five-oh-two".
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Motorola 68000
The Motorola 68000 ("'sixty-eight-thousand'"; also called the m68k or Motorola 68k, "sixty-eight-kay") is a 16/32-bit CISC microprocessor, which implements a 32-bit instruction set, with 32-bit registers and 32-bit internal data bus, but with a 16-bit data ALU and two 16-bit arithmetic ALUs and a 16-bit external data bus, designed and marketed by Motorola Semiconductor Products Sector.
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Motorola 68000 series
The Motorola 68000 series (also termed 680x0, m68000, m68k, or 68k) is a family of 32-bit CISC microprocessors.
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Multimedia Acceleration eXtensions
The Multimedia Acceleration eXtensions or MAX are instruction set extensions to the Hewlett-Packard PA-RISC instruction set architecture (ISA).
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NS320xx
The 320xx or NS32000 was a series of microprocessors from National Semiconductor.
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OpenRISC
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC) principles.
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Operand
In mathematics an operand is the object of a mathematical operation, i.e. it is the quantity that is operated on.
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PA-RISC
PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard.
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PDP-11
The PDP-11 is a series of 16-bit minicomputers sold by Digital Equipment Corporation (DEC) from 1970 into the 1990s, one of a succession of products in the PDP series.
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Physical Address Extension
In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension, is a memory management feature for the x86 architecture.
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PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM.
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Processor design
Processor design is the design engineering task of creating a processor, a component of computer hardware.
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Processor register
In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU).
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Reduced instruction set computer
A reduced instruction set computer, or RISC (pronounced 'risk'), is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
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Register file
A register file is an array of processor registers in a central processing unit (CPU).
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Register window
In computer engineering, register windows are a feature in some instruction set architectures to improve the performance of procedure calls, a very common operation.
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RISC-V
RISC-V (pronounced "risk-five") is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
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RX microcontroller family
RX is the family name for a range of 32-bit microcontrollers manufactured by Renesas Electronics.
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S+core
S+core is a hybrid 32/16-bit instruction set architecture designed by Sunplus Technology.
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SPARC
SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems.
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SSE2
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000.
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SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture.
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SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L).
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Stack machine
In computer science, computer engineering and programming language implementations, a stack machine is a type of computer.
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Streaming SIMD Extensions
In computing, Streaming SIMD Extensions (SSE) is an SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of processors shortly after the appearance of AMD's 3DNow!.
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SuperH
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas.
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Synopsys
Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry.
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Transmeta Crusoe
The Crusoe is a family of x86-compatible microprocessors developed by Transmeta and introduced in 2000.
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Transputer
The transputer is a series of pioneering microprocessors from the 1980s, featuring integrated memory and serial communication links, intended for parallel computing.
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VAX
VAX is a discontinued instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC) in the mid-1970s.
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Visual Instruction Set
Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems.
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X86
x86 is a family of backward-compatible instruction set architectures based on the Intel 8086 CPU and its Intel 8088 variant.
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X86-64
x86-64 (also known as x64, x86_64, AMD64 and Intel 64) is the 64-bit version of the x86 instruction set.
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X87
x87 is a floating point-related subset of the x86 architecture instruction set.
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XOP instruction set
The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011.
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Z/Architecture
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit instruction set architecture implemented by its mainframe computers.
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Zilog Z80
The Z80 CPU is an 8-bit based microprocessor.
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16-bit
16-bit microcomputers are computers in which 16-bit microprocessors were the norm.
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32-bit
32-bit microcomputers are computers in which 32-bit microprocessors are the norm.
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3DNow!
3DNow! is an extension to the x86 instruction set developed by Advanced Micro Devices (AMD).
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64-bit computing
In computer architecture, 64-bit computing is the use of processors that have datapath widths, integer size, and memory address widths of 64 bits (eight octets).
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8-bit
8-bit is also a generation of microcomputers in which 8-bit microprocessors were the norm.
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Comparison of CPU architectures, Comparison of cpu architectures, Comparison of instruction sets.
References
[1] https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures
