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12 relations: GNU General Public License, LEON, Microprocessor, Open-source hardware, Open-source model, OpenRISC, OpenSPARC, Programmable interrupt controller, SPARC, Sun Microsystems, UltraSPARC T1, Wishbone (computer bus).
GNU General Public License
The GNU General Public License (GNU GPL or GPL) is a widely used free software license, which guarantees end users the freedom to run, study, share and modify the software.
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LEON
LEON (from león, meaning lion) is a 32-bit CPU microprocessor core, based on the SuperSPARC SPARC-V8 RISC architecture and instruction set designed by Sun Microsystems.
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Microprocessor
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits.
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Open-source hardware
Open-source hardware (OSH) consists of physical artifacts of technology designed and offered by the open design movement.
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Open-source model
The open-source model is a decentralized software-development model that encourages open collaboration.
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OpenRISC
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC) principles.
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OpenSPARC
OpenSPARC is an open-source hardware project started in December 2005.
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Programmable interrupt controller
In computing, a programmable interrupt controller (PIC) is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs.
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SPARC
SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems.
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Sun Microsystems
Sun Microsystems, Inc. was an American company that sold computers, computer components, software, and information technology services and created the Java programming language, the Solaris operating system, ZFS, the Network File System (NFS), and SPARC.
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UltraSPARC T1
Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU.
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Wishbone (computer bus)
The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other.
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