Faster access than browser!
37 relations: Advanced Encryption Standard, Cache coherence, Central processing unit, CPU cache, Cyclic redundancy check, Data Encryption Standard, DDR3 SDRAM, Elliptic-curve cryptography, Finite field, Gigabit Ethernet, International Solid-State Circuits Conference, KASUMI, MD5, Microprocessor, Multi-core processor, Multithreading (computer architecture), OpenSolaris, Oracle Corporation, Oracle OpenWorld, Oracle VM Server for SPARC, PCI Express, RC4, RSA (cryptosystem), SHA-1, SHA-2, SPARC, SPARC Enterprise, SPARC T-Series, SPARC T4, SSL acceleration, Sun Microsystems, Symmetric multiprocessing, The Register, Triple DES, UltraSPARC T1, UltraSPARC T2, 10 Gigabit Ethernet.
Advanced Encryption Standard
The Advanced Encryption Standard (AES), also known by its original name Rijndael, is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001.
New!!: SPARC T3 and Advanced Encryption Standard · See more »
Cache coherence
In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches.
New!!: SPARC T3 and Cache coherence · See more »
Central processing unit
A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.
New!!: SPARC T3 and Central processing unit · See more »
CPU cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
New!!: SPARC T3 and CPU cache · See more »
Cyclic redundancy check
A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data.
New!!: SPARC T3 and Cyclic redundancy check · See more »
Data Encryption Standard
The Data Encryption Standard (DES) is a symmetric-key algorithm for the encryption of electronic data.
New!!: SPARC T3 and Data Encryption Standard · See more »
DDR3 SDRAM
Double data rate type three SDRAM (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007.
New!!: SPARC T3 and DDR3 SDRAM · See more »
Elliptic-curve cryptography
Elliptic-curve cryptography (ECC) is an approach to public-key cryptography based on the algebraic structure of elliptic curves over finite fields.
New!!: SPARC T3 and Elliptic-curve cryptography · See more »
Finite field
In mathematics, a finite field or Galois field (so-named in honor of Évariste Galois) is a field that contains a finite number of elements.
New!!: SPARC T3 and Finite field · See more »
Gigabit Ethernet
In computer networking, Gigabit Ethernet (GbE or 1 GigE) is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second (1,000,000,000 bits per second), as defined by the IEEE 802.3-2008 standard.
New!!: SPARC T3 and Gigabit Ethernet · See more »
International Solid-State Circuits Conference
International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip.
New!!: SPARC T3 and International Solid-State Circuits Conference · See more »
KASUMI
KASUMI is a block cipher used in UMTS, GSM, and GPRS mobile communications systems.
New!!: SPARC T3 and KASUMI · See more »
MD5
The MD5 algorithm is a widely used hash function producing a 128-bit hash value.
New!!: SPARC T3 and MD5 · See more »
Microprocessor
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC), or at most a few integrated circuits.
New!!: SPARC T3 and Microprocessor · See more »
Multi-core processor
A multi-core processor is a single computing component with two or more independent processing units called cores, which read and execute program instructions.
New!!: SPARC T3 and Multi-core processor · See more »
Multithreading (computer architecture)
In computer architecture, multithreading is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
New!!: SPARC T3 and Multithreading (computer architecture) · See more »
OpenSolaris
OpenSolaris is a discontinued, open source computer operating system based on Solaris created by Sun Microsystems.
New!!: SPARC T3 and OpenSolaris · See more »
Oracle Corporation
Oracle Corporation is an American multinational computer technology corporation, headquartered in Redwood Shores, California.
New!!: SPARC T3 and Oracle Corporation · See more »
Oracle OpenWorld
Oracle OpenWorld is an annual Oracle convention for business decision-makers, IT management, and line-of-business end users.
New!!: SPARC T3 and Oracle OpenWorld · See more »
Oracle VM Server for SPARC
Logical Domains (LDoms or LDOM) is the server virtualization and partitioning technology for SPARC V9 processors.
New!!: SPARC T3 and Oracle VM Server for SPARC · See more »
PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X, and AGP bus standards.
New!!: SPARC T3 and PCI Express · See more »
RC4
In cryptography, RC4 (Rivest Cipher 4 also known as ARC4 or ARCFOUR meaning Alleged RC4, see below) is a stream cipher.
New!!: SPARC T3 and RC4 · See more »
RSA (cryptosystem)
RSA (Rivest–Shamir–Adleman) is one of the first public-key cryptosystems and is widely used for secure data transmission.
New!!: SPARC T3 and RSA (cryptosystem) · See more »
SHA-1
In cryptography, SHA-1 (Secure Hash Algorithm 1) is a cryptographic hash function which takes an input and produces a 160-bit (20-byte) hash value known as a message digest - typically rendered as a hexadecimal number, 40 digits long.
New!!: SPARC T3 and SHA-1 · See more »
SHA-2
SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA).
New!!: SPARC T3 and SHA-2 · See more »
SPARC
SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems.
New!!: SPARC T3 and SPARC · See more »
SPARC Enterprise
The SPARC Enterprise series is a range of UNIX server computers based on the SPARC V9 architecture.
New!!: SPARC T3 and SPARC Enterprise · See more »
SPARC T-Series
The SPARC T-Series family of RISC processors and server computers, based on the SPARC V9 architecture, was originally developed by Sun Microsystems, and later by Oracle Corporation after its acquisition of Sun.
New!!: SPARC T3 and SPARC T-Series · See more »
SPARC T4
The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation.
New!!: SPARC T3 and SPARC T4 · See more »
SSL acceleration
SSL acceleration (TLS acceleration) is a method of offloading processor-intensive public-key encryption for Transport Layer Security (TLS) and its predecessor Secure Sockets Layer (SSL) to a hardware accelerator.
New!!: SPARC T3 and SSL acceleration · See more »
Sun Microsystems
Sun Microsystems, Inc. was an American company that sold computers, computer components, software, and information technology services and created the Java programming language, the Solaris operating system, ZFS, the Network File System (NFS), and SPARC.
New!!: SPARC T3 and Sun Microsystems · See more »
Symmetric multiprocessing
Symmetric multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory, have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes.
New!!: SPARC T3 and Symmetric multiprocessing · See more »
The Register
The Register (nicknamed El Reg) is a British technology news and opinion website co-founded in 1994 by Mike Magee, John Lettice and Ross Alderson.
New!!: SPARC T3 and The Register · See more »
Triple DES
In cryptography, Triple DES (3DES), officially the Triple Data Encryption Algorithm (TDEA or Triple DEA), is a symmetric-key block cipher, which applies the DES cipher algorithm three times to each data block.
New!!: SPARC T3 and Triple DES · See more »
UltraSPARC T1
Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU.
New!!: SPARC T3 and UltraSPARC T1 · See more »
UltraSPARC T2
Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU.
New!!: SPARC T3 and UltraSPARC T2 · See more »
10 Gigabit Ethernet
10 Gigabit Ethernet (10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10 gigabits per second.
New!!: SPARC T3 and 10 Gigabit Ethernet · See more »
Redirects here:
References
[1] https://en.wikipedia.org/wiki/SPARC_T3
