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35 relations: Addressing mode, Advanced Encryption Standard, Advanced Vector Extensions, APL (programming language), Array programming, Bit manipulation, Cannon Lake (microarchitecture), Cascade Lake (microarchitecture), CLMUL instruction set, EVEX prefix, Exponential function, Exponentiation, Finite field, FMA instruction set, Hamming weight, Ice Lake (microarchitecture), Instruction set architecture, Intel, Intel Advisor, Larrabee (microarchitecture), Multiplicative inverse, Multiply–accumulate operation, Significand, SIMD, Skylake (microarchitecture), SSE4, Streaming SIMD Extensions, Transcendental function, Truth table, VEX prefix, X86, Xeon Phi, XOP instruction set, 256-bit, 512-bit.
Addressing mode
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs.
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Advanced Encryption Standard
The Advanced Encryption Standard (AES), also known by its original name Rijndael, is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001.
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Advanced Vector Extensions
Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011.
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APL (programming language)
APL (named after the book A Programming Language) is a programming language developed in the 1960s by Kenneth E. Iverson.
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Array programming
In computer science, array programming languages (also known as vector or multidimensional languages) generalize operations on scalars to apply transparently to vectors, matrices, and higher-dimensional arrays.
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Bit manipulation
Bit manipulation is the act of algorithmically manipulating bits or other pieces of data shorter than a word.
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Cannon Lake (microarchitecture)
Cannon Lake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture.
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Cascade Lake (microarchitecture)
Cascade Lake is an Intel codename for a 14 nm server and enthusiast processor microarchitecture.
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CLMUL instruction set
Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010.
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EVEX prefix
The EVEX prefix (Enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit x86 (IA-32) and 64-bit x86-64 (AMD64) instruction set architecture.
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Exponential function
In mathematics, an exponential function is a function of the form in which the argument occurs as an exponent.
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Exponentiation
Exponentiation is a mathematical operation, written as, involving two numbers, the base and the exponent.
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Finite field
In mathematics, a finite field or Galois field (so-named in honor of Évariste Galois) is a field that contains a finite number of elements.
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FMA instruction set
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations.
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Hamming weight
The Hamming weight of a string is the number of symbols that are different from the zero-symbol of the alphabet used.
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Ice Lake (microarchitecture)
Ice Lake is the Intel CPU microarchitecture based on the 10 nm node that is expected to replace Coffee Lake and Cannon Lake in 2019.
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Instruction set architecture
An instruction set architecture (ISA) is an abstract model of a computer.
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Intel
Intel Corporation (stylized as intel) is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley.
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Intel Advisor
Intel Advisor (also known as "Advisor XE", "Vectorization Advisor" or "Threading Advisor") is a SIMD vectorization optimization and shared memory threading assistance tool for C, C++, C# and Fortran software developers and architects.
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Larrabee (microarchitecture)
Larrabee is the codename for a cancelled GPGPU chip that Intel was developing separately from its current line of integrated graphics accelerators.
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Multiplicative inverse
In mathematics, a multiplicative inverse or reciprocal for a number x, denoted by 1/x or x−1, is a number which when multiplied by x yields the multiplicative identity, 1.
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Multiply–accumulate operation
In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator.
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Significand
The significand (also mantissa or coefficient) is part of a number in scientific notation or a floating-point number, consisting of its significant digits.
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SIMD
Single instruction, multiple data (SIMD) is a class of parallel computers in Flynn's taxonomy.
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Skylake (microarchitecture)
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture.
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SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L).
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Streaming SIMD Extensions
In computing, Streaming SIMD Extensions (SSE) is an SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of processors shortly after the appearance of AMD's 3DNow!.
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Transcendental function
A transcendental function is an analytic function that does not satisfy a polynomial equation, in contrast to an algebraic function.
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Truth table
A truth table is a mathematical table used in logic—specifically in connection with Boolean algebra, boolean functions, and propositional calculus—which sets out the functional values of logical expressions on each of their functional arguments, that is, for each combination of values taken by their logical variables (Enderton, 2001).
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VEX prefix
The VEX prefix (from "vector extensions") and VEX coding scheme are comprising an extension to the x86 and x86-64 instruction set architecture for microprocessors from Intel, AMD and others.
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X86
x86 is a family of backward-compatible instruction set architectures based on the Intel 8086 CPU and its Intel 8088 variant.
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Xeon Phi
Xeon Phi is a series of x86 manycore processors designed and made entirely by Intel.
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XOP instruction set
The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011.
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256-bit
There are currently no mainstream general-purpose processors built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data.
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512-bit
There are currently no mainstream general-purpose processors built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data.
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Redirects here:
AVX3, AVX512, Advanced Vector Extensions 512, VNNI.
References
[1] https://en.wikipedia.org/wiki/AVX-512
