Branch target predictor

In computer architecture, a branch target predictor is the part of a processor that predicts the target of a taken conditional branch or an unconditional branch instruction before the target of the branch instruction is computed by the execution unit of the processor. ^[1]

7 relations: Branch (computer science), Branch predictor, Computer architecture, CPU cache, CPUID, Instruction cycle, Parallel computing.

Branch (computer science)

A branch is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order.

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Branch predictor

In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively.

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Computer architecture

In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.

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CPU cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.

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CPUID

The CPUID opcode is a processor supplementary instruction (its name derived from CPU IDentification) for the x86 architecture allowing software to discover details of the processor.

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Instruction cycle

An instruction cycle (also known as the fetch–decode–execute cycle or the fetch-execute cycle) is the basic operational process of a computer.

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Parallel computing

Parallel computing is a type of computation in which many calculations or the execution of processes are carried out concurrently.

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Redirects here:

Branch target buffer.

References

[1] https://en.wikipedia.org/wiki/Branch_target_predictor

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