129 relations: Address space, Advanced Micro Devices, Alpha 21164, Alpha 21264, Alpha particle, AMD K6-2, AMD K6-III, AnandTech, Athlon, Athlon 64, Atlas (computer), Basic block, Birthday problem, Bit numbering, Branch predictor, Bulldozer (microarchitecture), Bus snooping, Cache (computing), Cache coherence, Cache control instruction, Cache hierarchy, Cache performance measurement and metric, Cache prefetching, Cache replacement policies, Central processing unit, Classic RISC pipeline, Computer, Computer data storage, Content-addressable memory, Context switch, CPU cache, Cray-1, Data (computing), Desktop computer, Digital Equipment Corporation, Dinero (cache simulator), Direct memory access, Dirty bit, Dual in-line package, Dynamic random-access memory, EDRAM, Electric energy consumption, Emitter-coupled logic, Error correction code, Ferranti, Frequency, GE 645, General Electric, Gibibyte, Hash function, ..., Haswell (microarchitecture), Heuristic, Homonym, Hyper-threading, IBM, IBM System/360 Model 67, IBM z13 (microprocessor), Instruction pipelining, Instruction set architecture, Instruction unit, Intel, Intel 80386, Intel 80486, Intel HD, UHD and Iris Graphics, Itanium, Ivy Bridge (microarchitecture), Kibibyte, Latency (engineering), List of Intel Core i7 microprocessors, Locality of reference, Loop nest optimization, Low-power electronics, Mebibyte, Memoization, Memory address, Memory cell (computing), Memory hierarchy, Memory management unit, Micro-operation, Microarchitecture, MIPS architecture, Motorola 68010, Motorola 68020, Motorola 68030, Motorola 68040, Motorola 68060, Multi-chip module, Multi-core processor, Multiprocessing, Out-of-order execution, P5 (microarchitecture), P6 (microarchitecture), Page table, Parity bit, Pentium 4, Pentium II, Pentium III, Pentium Pro, Phase-change memory, POWER4, Processor register, R6000, Random-access memory, Register file, Register renaming, Resistive random-access memory, Sandy Bridge, Scratchpad memory, Server (computing), Simultaneous multithreading, Skylake (microarchitecture), Socket 7, Speculative execution, Spin-transfer torque, Static random-access memory, Sum addressed decoder, Supercomputer, Synchronous dynamic random-access memory, Synonym, Trade-off, Translation lookaside buffer, University of Wisconsin System, VHDL, Victim cache, Virtual memory, Write buffer, X86, Xeon, Zen (microarchitecture). Expand index (79 more) » « Shrink index
In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity.
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets.
The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA).
The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor introduced in October, 1996.
Alpha particles consist of two protons and two neutrons bound together into a particle identical to a helium-4 nucleus.
The K6-2 is an x86 microprocessor introduced by AMD on May 28, 1998, and available in speeds ranging from 266 to 550 MHz.
The K6-III, code-named "Sharptooth", is an x86 microprocessor manufactured by AMD, released on 22 February 1999, with 400 and 450 MHz models.
AnandTech is an online computer hardware magazine.
Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices (AMD).
The Athlon 64 is an eighth-generation, AMD64-architecture microprocessor produced by AMD, released on September 23, 2003.
The Atlas Computer was a joint development between the University of Manchester, Ferranti, and Plessey.
In compiler construction, a basic block is a straight-line code sequence with no branches in except to the entry and no branches out except at the exit.
In probability theory, the birthday problem or birthday paradox concerns the probability that, in a set of randomly chosen people, some pair of them will have the same birthday.
In computing, bit numbering (or sometimes bit endianness) is the convention used to identify the bit positions in a binary number or a container for such a value.
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively.
The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets.
Bus snooping or bus sniffing is a scheme that a coherency controller (snooper) in a cache monitors or snoops the bus transactions, and its goal is to maintain a cache coherency in distributed shared memory systems.
In computing, a cache, is a hardware or software component that stores data so future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation, or the duplicate of data stored elsewhere.
In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches.
In computing, a cache control instruction is a hint embedded in the instruction stream of a processor intended to improve the performance of hardware caches, using foreknowledge of the memory access pattern supplied by the programmer or compiler.
Cache hierarchy, or multi-level caches, refers to a memory design property which uses a hierarchy of memory stores based on varying access speeds to cache data.
The CPU cache is a piece of hardware which reduces the access time to the data in the memory by keeping some part of the frequently used data of the main memory in itself.
Cache prefetching is a technique used by computer processors to boost execution performance by fetching instructions or data from their original storage in slower memory to a faster local memory before it is actually needed (hence the term 'prefetch').
In computing, cache algorithms (also frequently called cache replacement algorithms or cache replacement policies) are optimizing instructionsor algorithmsthat a computer program or a hardware-maintained structure can follow in order to manage a cache of information stored on the computer.
A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.
In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline.
A computer is a device that can be instructed to carry out sequences of arithmetic or logical operations automatically via computer programming.
Computer data storage, often called storage or memory, is a technology consisting of computer components and recording media that are used to retain digital data.
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications.
In computing, a context switch is the process of storing the state of a process or of a thread, so that it can be restored and execution resumed from the same point later.
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
The Cray-1 was a supercomputer designed, manufactured and marketed by Cray Research.
Data (treated as singular, plural, or as a mass noun) is any sequence of one or more symbols given meaning by specific act(s) of interpretation.
A desktop computer is a personal computer designed for regular use at a single location on or near a desk or table due to its size and power requirements.
Digital Equipment Corporation, also known as DEC and using the trademark Digital, was a major American company in the computer industry from the 1950s to the 1990s.
Dinero is a uniprocessor CPU cache simulator for memory reference traces written by Dr.
Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (Random-access memory), independent of the central processing unit (CPU).
A dirty bit or modified bit is a bit that is associated with a block of computer memory and indicates whether or not the corresponding block of memory has been modified.
In microelectronics, a dual in-line package (DIP or DIL), or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins.
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a separate tiny capacitor within an integrated circuit.
Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor.
Electric energy consumption is the form of energy consumption that uses electric energy.
In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family.
In computing, telecommunication, information theory, and coding theory, an error correction code, sometimes error correcting code, (ECC) is used for controlling errors in data over unreliable or noisy communication channels.
Ferranti or Ferranti International plc was a UK electrical engineering and equipment firm that operated for over a century from 1885 until it went bankrupt in 1993.
Frequency is the number of occurrences of a repeating event per unit of time.
The GE 645 mainframe computer was a development of the GE 635 for use in the Multics project.
General Electric Company (GE) is an American multinational conglomerate incorporated in New York and headquartered in Boston, Massachusetts.
The gibibyte is a multiple of the unit byte for digital information.
A hash function is any function that can be used to map data of arbitrary size to data of a fixed size.
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge microarchitecture.
A heuristic technique (εὑρίσκω, "find" or "discover"), often called simply a heuristic, is any approach to problem solving, learning, or discovery that employs a practical method, not guaranteed to be optimal, perfect, logical, or rational, but instead sufficient for reaching an immediate goal.
In linguistics, homonyms, broadly defined, are words which sound alike or are spelled alike, but have different meanings.
Hyper-threading (officially called Hyper-Threading Technology or HT Technology, and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors.
The International Business Machines Corporation (IBM) is an American multinational technology company headquartered in Armonk, New York, United States, with operations in over 170 countries.
The IBM System/360 Model 67 (S/360-67) was an important IBM mainframe model in the late 1960s.
The z13 is a microprocessor made by IBM for their z13 mainframe computers, announced on January 14, 2015.
Instruction pipelining is a technique for implementing instruction-level parallelism within a single processor.
An instruction set architecture (ISA) is an abstract model of a computer.
The instruction unit (IU) in a central processing unit (CPU) is responsible for organising program instructions to be fetched from memory, and executed, in an appropriate order.
Intel Corporation (stylized as intel) is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley.
The Intel 80386, also known as i386 or just 386, is a 32-bit microprocessor introduced in 1985.
The Intel 80486, also known as the i486 or 486, is a higher performance follow-up to the Intel 80386 microprocessor.
Intel HD Graphics is a series of integrated graphics processors (IGPs) introduced by Intel in 2010 that are manufactured on the same package or die as the central processing unit (CPU).
Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64).
Ivy Bridge is the codename for the "third generation" of the Intel Core processors (Core i7, i5, i3).
The kibibyte is a multiple of the unit byte for quantities of digital information.
Latency is a time interval between the stimulation and response, or, from a more general point of view, a time delay between the cause and the effect of some physical change in the system being observed.
The following is a list of Intel Core i7 brand microprocessors.
In computer science, locality of reference, also known as the principle of locality, is a term for the phenomenon in which the same values, or related storage locations, are frequently accessed, depending on the memory access pattern.
In computer science and particularly in compiler design, loop nest optimization (LNO) is an optimization technique that applies a set of loop transformations for the purpose of locality optimization or parallelization or other loop overhead reduction of the loop nests.
Low-power electronics are electronics, such as notebook processors, that have been designed to use less electric power.
The mebibyte is a multiple of the unit byte for digital information.
In computing, memoization or memoisation is an optimization technique used primarily to speed up computer programs by storing the results of expensive function calls and returning the cached result when the same inputs occur again.
In computing, a memory address is a reference to a specific memory location used at various levels by software and hardware.
The memory cell is the fundamental building block of computer memory.
In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time.
A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.
In computer central processing units, micro-operations (also known as a micro-ops or μops) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).
In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA), is implemented in a particular processor.
MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA)Price, Charles (September 1995).
The Motorola MC68010 processor is a 16/32-bit microprocessor from Motorola, released in 1982 as the successor to the Motorola 68000.
The Motorola 68020 ("sixty-eight-oh-twenty", "sixty-eight-oh-two-oh" or "six-eight-oh-two-oh") is a 32-bit microprocessor from Motorola, released in 1984.
The Motorola 68030 ("sixty-eight-oh-thirty") is a 32-bit microprocessor in the Motorola 68000 family.
The Motorola 68040 ("sixty-eight-oh-forty") is a 32-bit microprocessor from Motorola, released in 1990.
The Motorola 68060 ("sixty-eight-oh-sixty") is a 32-bit microprocessor from Motorola released in 1994.
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it is treated as if it were a single component (as though a larger IC).
A multi-core processor is a single computing component with two or more independent processing units called cores, which read and execute program instructions.
Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system.
In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted.
The first Pentium microprocessor was introduced by Intel on March 22, 1993.
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995.
A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.
A parity bit, or check bit, is a bit added to a string of binary code to ensure that the total number of 1-bits in the string is even or odd.
Pentium 4 is a brand by Intel for an entire series of single-core CPUs for desktops, laptops and entry-level servers.
The Pentium II brand refers to Intel's sixth-generation microarchitecture ("P6") and x86-compatible microprocessors introduced on May 7, 1997.
The Pentium III (marketed as Intel Pentium III Processor, informally PIII) brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999.
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995.
Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (ovonic unified memory) and C-RAM or CRAM (chalcogenide RAM)) is a type of non-volatile random-access memory.
The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures.
In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU).
The R6000, not to be confused with the IBM RAD6000, is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II instruction set architecture (ISA).
Random-access memory (RAM) is a form of computer data storage that stores data and machine code currently being used.
A register file is an array of processor registers in a central processing unit (CPU).
In computer architecture, register renaming is a technique that eliminates the false data dependencies arising from the reuse of architectural registers by successive instructions that do not have any real data dependencies between them.
Resistive random-access memory (ReRAM or RRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material, often referred to as a memristor.
Sandy Bridge is the codename for the microarchitecture used in the "second generation" of the Intel Core processors (Core i7, i5, i3) - the Sandy Bridge microarchitecture is the successor to Nehalem microarchitecture.
Scratchpad memory (SPM), also known as scratchpad, scratchpad RAM or local store in computer terminology, is a high-speed internal memory used for temporary storage of calculations, data, and other work in progress.
In computing, a server is a computer program or a device that provides functionality for other programs or devices, called "clients".
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading.
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture.
Socket 7 is a physical and electrical specification for an x86-style CPU socket on a personal computer motherboard.
Speculative execution is an optimization technique where a computer system performs some task that may not be needed.
Spin-transfer torque is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be modified using a spin-polarized current.
Static random-access memory (static RAM or SRAM) is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit.
In CPU design, the use of a Sum Addressed Decoder (SAD) or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access.
A supercomputer is a computer with a high level of performance compared to a general-purpose computer.
Synchronous dynamic random-access memory (SDRAM) is any dynamic random-access memory (DRAM) where the operation of its external pin interface is coordinated by an externally supplied clock signal.
A synonym is a word or phrase that means exactly or nearly the same as another word or phrase in the same language.
A trade-off (or tradeoff) is a situational decision that involves diminishing or losing one quality, quantity or property of a set or design in return for gains in other aspects.
A translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location.
The University of Wisconsin System is a university system of public universities in the state of Wisconsin.
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
A victim cache is a small, usually fully associative cache placed in the refill path of CPU cache, and it stores all the blocks evicted from that level of cache.
In computing, virtual memory (also virtual storage) is a memory management technique that provides an "idealized abstraction of the storage resources that are actually available on a given machine" which "creates the illusion to users of a very large (main) memory." The computer's operating system, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses in computer memory.
A write buffer is a type of data buffer used in certain CPU cache architectures like Intel's x86 and AMD64.
x86 is a family of backward-compatible instruction set architectures based on the Intel 8086 CPU and its Intel 8088 variant.
Xeon is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets.
Zen is the codename for a computer processor microarchitecture from AMD, and was first used with their Ryzen series of CPUs in February 2017.
Associative cache, Branch target cache, Branch target instruction cache, CPU Cache, CPU cache line, CPU caches, CPU memory cache, Cache Memory, Cache associativity, Cache block, Cache eviction, Cache flush, Cache line, Cache lines, Cache memory, Cache miss, Cache-line, Copy-back, Cpu cache, Data Cache, Direct mapped, Discrete L2 cache, Exclusive CPU cache, Exclusive cache, First-level cache, Full associative, Fully associative, Fully associative cache, I cache, Inclusive CPU cache, Inclusive cache, Instruction cache, Internal and external cache, Internal cache, L1 cache, L1-Cache, L2 Cache, L2 cache, L2-Cache, L3 cache, L4 cache, Last Level Cache, Last level cache, Level 1 cache, Level 2 cache, Level 3 cache, Micro-operation cache, Motherboard cache, Multi-level cache, Multi-ported Cache, Multilevel cache, Non-blocking cache, On-chip cache, PIPT, Processor cache, Second-level cache, Secondary cache, Set associative, Set associative cache, Set-associative, Set-associativity, Shared cache, Tag RAM, Trace Caches, Trace caches, Uop cache, VIPT, VIVT.