40 relations: Advanced Vector Extensions, AES instruction set, Broadwell (microarchitecture), Cannon Lake (microarchitecture), CLMUL instruction set, Clock rate, DDR4 SDRAM, Desktop, DisplayPort, FinFET, FMA instruction set, HDMI, High-bandwidth Digital Content Protection, Hyper-threading, Ice Lake (microarchitecture), Instructions per cycle, Intel, Intel HD, UHD and Iris Graphics, Intel Turbo Boost, Kaby Lake, LGA 1151, List of Intel codenames, List of Intel CPU microarchitectures, MMX (instruction set), Multi-channel memory architecture, Pinout, Skylake (microarchitecture), Software Guard Extensions, SSE2, SSE3, SSE4, SSSE3, Streaming SIMD Extensions, Thermal design power, Transactional Synchronization Extensions, Trusted Execution Technology, Whiskey Lake (microarchitecture), X86 virtualization, X86-64, 14 nanometer.
Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011.
Advanced Encryption Standard instruction set (or the Intel Advanced Encryption Standard New Instructions; AES-NI) is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.
Broadwell is Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture.
Cannon Lake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture.
Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010.
The clock rate typically refers to the frequency at which a chip like a central processing unit (CPU), one core of a multi-core processor, is running and is used as an indicator of the processor's speed.
In computing, DDR4 SDRAM, an abbreviation for double data rate fourth-generation synchronous dynamic random-access memory, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface.
Desktop may refer to.
DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA).
A Fin Field-effect transistor (FinFET) is a MOSFET tri-gate transistor built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure.
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations.
HDMI (High-Definition Multimedia Interface) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, to a compatible computer monitor, video projector, digital television, or digital audio device.
High-bandwidth Digital Content Protection (HDCP) is a form of digital copy protection developed by Intel Corporation to prevent copying of digital audio & video content as it travels across connections.
Hyper-threading (officially called Hyper-Threading Technology or HT Technology, and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors.
Ice Lake is the Intel CPU microarchitecture based on the 10 nm node that is expected to replace Coffee Lake and Cannon Lake in 2019.
In computer architecture, instructions per cycle (IPC) is one aspect of a processor's performance: the average number of instructions executed for each clock cycle.
Intel Corporation (stylized as intel) is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley.
Intel HD Graphics is a series of integrated graphics processors (IGPs) introduced by Intel in 2010 that are manufactured on the same package or die as the central processing unit (CPU).
Intel Turbo Boost is Intel's trade name for a feature that automatically raises certain of its processors' operating frequency, and thus performance, when demanding tasks are running.
Kaby Lake is an Intel codename for a processor microarchitecture Intel announced on August 30, 2016.
LGA 1151, also known as Socket H4, is an Intel microprocessor compatible socket which comes in two distinct versions: the first revision which supports both Intel's Skylake and Kaby Lake CPUs, and the second revision which supports Coffee Lake CPUs exclusively.
Intel has historically named integrated circuit (IC) development projects after geographical names of towns, rivers or mountains near the location of the Intel facility responsible for the IC.
The following is a partial list of Intel CPU microarchitectures.
MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1997 with its P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology".
In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication between them.
In electronics, a pinout (sometimes written "pin-out") is a cross-reference between the contacts, or pins, of an electrical connector or electronic component, and their functions.
Skylake is the codename used by Intel for a processor microarchitecture that was launched in August 2015 succeeding the Broadwell microarchitecture.
Intel SGX is a set of central processing unit (CPU) instruction codes from Intel that allows user-level code to allocate private regions of memory, called enclaves, that are protected from processes running at higher privilege levels.
SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000.
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture.
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L).
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
In computing, Streaming SIMD Extensions (SSE) is an SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of processors shortly after the appearance of AMD's 3DNow!.
The thermal design power (TDP), sometimes called thermal design point, is the maximum amount of heat generated by a computer chip or component (often the CPU or GPU) that the cooling system in a computer is designed to dissipate under any workload.
Transactional Synchronization Extensions (TSX-NI) is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding up execution of multi-threaded software through lock elision.
Intel Trusted Execution Technology (Intel TXT, formerly known as LaGrande Technology) is a computer hardware technology whose primary goals are.
Whiskey Lake is Intel's codename for the third 14 nm Skylake process-refinement, following Kaby Lake and Coffee Lake.
In computing, x86 virtualization refers to hardware virtualization for the x86 architecture.
x86-64 (also known as x64, x86_64, AMD64 and Intel 64) is the 64-bit version of the x86 instruction set.
The 14 nanometer (14 nm) semiconductor device fabrication node is the technology node following the 22 nm/(20 nm) node.