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Multi-master bus

Index Multi-master bus

A multi-master bus is a computer bus in which there are multiple bus master nodes present on the bus. [1]

5 relations: Bus (computing), Bus mastering, Central processing unit, Direct memory access, I²C.

Bus (computing)

In computer architecture, a bus (a contraction of the Latin omnibus) is a communication system that transfers data between components inside a computer, or between computers.

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Bus mastering

In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions.

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Central processing unit

A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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Direct memory access

Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (Random-access memory), independent of the central processing unit (CPU).

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I²C

I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a synchronous, multi-master, multi-slave, packet switched, single-ended, serial computer bus invented in 1982 by Philips Semiconductor (now NXP Semiconductors).

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Redirects here:

Multi master bus, Multi-master architecture, Multimaster bus.

References

[1] https://en.wikipedia.org/wiki/Multi-master_bus

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