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14 relations: Automatic test pattern generation, Chip-scale package, Contact pad, CPU cache, Die preparation, Integrated circuit, Integrated circuit packaging, Non-contact wafer testing, Probe card, Semiconductor device fabrication, Substrate mapping, Wafer bond characterization, Wafer bonding, Wafer testing.
Automatic test pattern generation
ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects.
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Chip-scale package
A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.
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Contact pad
Contact pads or bond pads are designated surface areas of a printed circuit board or die of an integrated circuit.
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CPU cache
A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
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Die preparation
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing.
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Integrated circuit
An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon.
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Integrated circuit packaging
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the tiny block of semiconducting material is encapsulated in a supporting case that prevents physical damage and corrosion.
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Non-contact wafer testing
Wafer testing is a normal step in semiconductor device fabrication, used to detect defects in integrated circuits (IC) before they are assembled during the IC packaging step.
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Probe card
A probe card is an interface between an electronic test system and a semiconductor wafer.
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Semiconductor device fabrication
Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices.
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Substrate mapping
Substrate mapping (or wafer mapping) is a process in which the performance of semiconductor devices on a substrate is represented by a map showing the performance as a colour-coded grid.
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Wafer bond characterization
The wafer bond characterization is based on different methods and tests.
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Wafer bonding
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed encapsulation.
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Wafer testing
Wafer testing is a step performed during semiconductor device fabrication.
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