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Predication (computer architecture)

Index Predication (computer architecture)

In computer science, predication is an architectural feature that provides an alternative to conditional branch instructions. [1]

23 relations: ARM architecture, Branch (computer science), Branch predictor, CDC Cyber, Conditional (computer programming), David August, DEC Alpha, Delay slot, Explicitly parallel instruction computing, Hazard (computer architecture), High-Level Shading Language, History of mathematical notation, IA-64, Instruction scheduling, Instruction set architecture, MIPS architecture, Pipeline stall, PowerPC, Predicate, RISC-V, Samplesort, Software pipelining, XOP instruction set.

ARM architecture

ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments.

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Branch (computer science)

A branch is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order.

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Branch predictor

In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively.

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CDC Cyber

The CDC Cyber range of mainframe-class supercomputers were the primary products of Control Data Corporation (CDC) during the 1970s and 1980s.

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Conditional (computer programming)

In computer science, conditional statements, conditional expressions and conditional constructs are features of a programming language, which perform different computations or actions depending on whether a programmer-specified boolean condition evaluates to true or false.

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David August

David I. August (born 1970) is a professor of computer science at Princeton University specializing in compilers and computer architecture.

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DEC Alpha

Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 32-bit VAX complex instruction set computer (CISC) ISA.

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Delay slot

In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction.

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Explicitly parallel instruction computing

Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the HP–Intel alliance to describe a computing paradigm that researchers had been investigating since the early 1980s.

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Hazard (computer architecture)

In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results.

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High-Level Shading Language

The High-Level Shader Language or High-Level Shading Language (HLSL) is a proprietary shading language developed by Microsoft for the Direct3D 9 API to augment the shader assembly language, and went on to become the required shading language for the unified shader model of Direct3D 10 and higher.

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History of mathematical notation

The history of mathematical notation includes the commencement, progress, and cultural diffusion of mathematical symbols and the conflict of the methods of notation confronted in a notation's move to popularity or inconspicuousness.

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IA-64 (also called Intel Itanium architecture) is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors.

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Instruction scheduling

In computer science, instruction scheduling is a compiler optimization used to improve instruction-level parallelism, which improves performance on machines with instruction pipelines.

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Instruction set architecture

An instruction set architecture (ISA) is an abstract model of a computer.

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MIPS architecture

MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA)Price, Charles (September 1995).

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Pipeline stall

In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard.

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PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM.

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Predicate or predication may refer to.

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RISC-V (pronounced "risk-five") is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.

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Samplesort is a sorting algorithm that is a divide and conquer algorithm often used in parallel processing systems.

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Software pipelining

In computer science, software pipelining is a technique used to optimize loops, in a manner that parallels hardware pipelining.

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XOP instruction set

The XOP (eXtended Operations) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011.

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Redirects here:

Branch Predication, Branch predication, Conditional move, Conditional moves.


[1] https://en.wikipedia.org/wiki/Predication_(computer_architecture)

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